1. Field of the Invention
The present invention relates in general to a method for fabricating a liquid crystal display (LCD), and specifically to a method comprising a boundary region being divided into a first mask and a second mask to suppress shot mura.
2. Description of the Related Art
FIG. 1 illustrates the circuit diagram of the pixel in a conventional thin film transistor liquid crystal display (abbreviated as TFT-LCD in the following description). As shown in FIG. 1, the circuits comprise a common electrode COM, a data line DL, a scan line GL, a thin film transistor Tx, a storage capacitor Cst, and a liquid crystal cell Clc. The data line DL is coupled to the source terminal S of the thin film transistor Tx. The scan line GL is coupled to the gate terminal G of the thin film transistor Tx. One terminal of the storage capacitor Cst is coupled to the drain terminal D of the thin film transistor Tx, while the other terminal of the storage capacitor Cst is coupled to the common electrode COM or the gate line of the adjacent pixel depending on the application. One terminal of the liquid crystal cell Clc is coupled to the drain terminal D of the thin film transistor Tx, while the other terminal of the liquid crystal cell Clc is coupled to the common electrode COM. In addition, there is a parasitic capacitor Cgd between the gate terminal G and the drain terminal D of the thin film transistor.
FIG. 2 illustrates the plane view of the conventional active matrix type TFT-LCD configuration. The TFT-LCD shown in FIG. 2 is comprised of a plurality of pixels, shown in FIG. 1, in an array configuration.
As the screen size of the TFT-LCD increases, the pattern of the essential circuits and devices are divided into several photo masks to fabricate a TFT-LCD. As shown in FIG. 2, the regions I and II are defined by photo masks A and B, respectively, and BL is the boundary line of the photo mask A and B. As is known from FIG. 2, the gate and drain/source electrodes are formed using different masks A and B. Since there is an overlay-offset or misalignment issue, the area in which the gate overlaps the source/drain (S/D) in a thin film transistor is different in size on both sides of the boundary line BL. This makes the overlapping capacitance Cgd different, leading to the shot mura phenomenon.
FIG. 3 illustrates the layout of the pixels, shown in FIG. 2, on both sides of the boundary line BL. In FIG. 3, 30 stands for a gate line and 32 stands for a data line. In the thin film transistors, the size of the areas which the gate line 30 overlaps the drains D are Agd—A and Agd—B, respectively, and the corresponding capacitances are Cgd—A and Cgd—B. Therefore, the feedthrough voltages of the pixels on both sides of the boundary line are,             Δ      ⁢                          ⁢              V        p_A              =                                        Δ            ⁢                                                  ⁢                          V              g                        ×                          C              gd_A                                            C            total_A                          ⁢                                  ⁢        and        ⁢                                  ⁢        Δ        ⁢                                  ⁢                  V          p_B                    =                        Δ          ⁢                                          ⁢                      V            g                    ×                      C            gd_B                                    C          total_B                      ;                wherein, Ctotal—A≈CSt+Clc+Cgd—A, Ctotal—B≈CSt+Clc+Cgd—B; ΔVg stands for the difference in the gate voltage when the TFT is turned on or turned off.        
Assuming that Ctotal—A=Ctotal—B=Ctotal, the difference in the feedthrough voltage of the pixels on both sides of the boundary line BL is,                                                         Δ              ⁢                                                          ⁢                              V                p_A                                      -                          Δ              ⁢                                                          ⁢                              V                p_B                                              =                                                                      Δ                  ⁢                                                                          ⁢                                      V                    g                                    ×                                      C                    gd_A                                                                    C                  total_A                                            -                                                Δ                  ⁢                                                                          ⁢                                      V                    g                                    ×                                      C                    gd_B                                                                    C                  total_B                                                      =                          Δ              ⁢                                                          ⁢                              V                g                            ×                                                                    C                    gd_A                                    -                                      C                    gd_B                                                                    C                  total                                                                    ;                            (        1        )            
According to the experimental results, if the difference in the feedthrough voltage is greater than 5 mV, the shot mura is visible with the naked eye.
In conventional methods for fabricating a TFT with A and B masks (or with more masks), such as U.S. Pat. No. 5,795,686, U.S. Pat. No. 5,656,526, U.S. Pat. No. 6,157,433, U.S. Pat. No. 5,945,256, and so on, the gate and drain/source electrodes are exposed using different masks A and B, and therefore the shot mura phenomenon inevitably occurs. If the difference in the feedthrough voltage of the pixels on both sides of the boundary line can be minimized, immunity to the shot mura phenomenon can be increased.